The GS9002 is a monolithic bipolar integrated circuit designed to serialize SMPTE 125M and SMPTE 244M bit parallel digital signals as well as other 8 or 10 bit parallel formats. This device performs the functions of sync detection, parallel to serial conversion, data scrambling (using the X9 + X4 +1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. It supports any of four selectable serial data rates from 100Mb/s to over 360Mb/s. The data rates are set by resistors and are selected by an on-board 2:4 decoder having two TTL level input address lines.
Other features such as a sync detector output, a sync detector disable input, and a lock detect output are also provided. The X9 + X4 + 1 scrambler and NRZ to NRZI converter may be bypassed to allow the output of the parallel to serial converter to be directly routed to the output drivers.
The GS9002 provides pseudo-ECL outputs for the serial data and serial clock as well as a single-ended pseudo-ECL output of the regenerated parallel clock.
The GS9002 directly interfaces with cable drivers GS9007, GS9008 and GS9009. The device requires a single +5 volt or -5 volt supply and typically consumes 713mW of power while driving 100 Ohm loads. The 44 pin PLCC packaging assures a small footprint for the complete encoder function.
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